Evaluation of contrast limited adaptive histogram equalization (CLAHE) enhancement on a FPGA

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Abstract
This paper presents the CLAHE method of contrast
enhancement targeted to a FPGA based embedded
platform. A novel approach to constructing the algo-
rithm utilizing FPGA resources is discussed. A com-
parative accuracy analysis is performed against the
equivalent software implementation. The FPGA re-
sources and operational power consumption are also
highlighted in the considerations required to include
effective contrast enhancement on a FPGA video
chain.
I INTRODUCTION
Adaptive histogram equalization (AHE) splits an im-
age into tiles and creates an intensity remapping
function from the accumulation of the histogram of
that tile. To smooth inter-tile boundaries the intensity
remapping is performed using bilinear interpolation.
This has the unfortunate effect of also enhancing the
noise content in background homogeneous regions.
Many methods [1] have been devised to minimize this
effect through a series of region weightings or modi-
fications to the cumulative function.
Contrast limited AHE [2] limits the noise enhance-
ment by establishing a maximum value (clip limit) a
bin can hold in the histogram of an image tile. This
creates an overflow from the clipped bins that must
be redistributed over the histogram of that tile. Ac-
cumulating this redistributed histogram reduces the
gradient of the remapping function, preserving dom-
inant intensities. This contrast enhancement tech-
nique has been predominantly placed in the medi-
cal imaging area, thus implementations have been
targeted to general purpose processor workstations.
At present there has been very few investigations

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